Analog circuits design and implementation of neuromorphic computing systems with advanced CMOS technologies

In the recent years, we have been faced with an impressive growth in the wireless communication systems and the data processing applications performed in the smart phones. People are using Internet every day and transfer data. To process these huge amount of information and keep progressing in the communication area, new and more complex computing paradigms are needed which traditionally are designed by the von Neumann architectures in the CMOS technology. However, the more progress in the communication systems means the more complicated and power-consuming applications are created and the less efficient the conventional processors will be. To enhance the performance of the traditional CMOS-based architectures in terms of power consumption and size, shrinking the device dimension has been a solution for the last five decades. Based on the Moor’s law, the channel length of the transistors halves per 18 months so that the new generations of the processors encompass more than one million transistors. However, we have reached the end of this roadmap and scaling down the device dimensions is not economically and technologically possible. In addition, the supply voltage can not be scaled down in the same rate as the channel length. This is because of the sub-threshold slope of the CMOS technology limited to 60 mV/decade . Therefore, the power consumption can not be reduced anymore through the scaling trend. These problems have motivated the researchers to benefit from emerging technologies and new device physics in order to tackle with the sub-threshold slope limitation, inefficiencies of the old von-Neumann computers, and improve the overall performance of the high-level computing paradigms. This thesis will focus on two advanced technologies named the Negative Capacitance Field Effect Transistor (NCFET) and Fully Depleted Silicon on Insulator (FDSOI) and show their benefits in the analog and mixed-signal designs. Furthermore, the sub-micron devices suffer from the short channel effects. Hot Carrier Injection (HCI) is the most important phenomenon in the nano-scale devices causing the reliability problems and the degradation of the device performance. The reliability problems are more severe in high frequencies. If reliability is considered from the beginning of the design phase, intelligent sweet-spots can be identified which deliver both reasonable performance and reliability. Therefore, this thesis shows the trade-off between the reliability and the circuit performance also.