Design and analysis of a carrier synchronization system using phase-locked loop

Carrier synchronization in highly dynamic environments can be a challenging problem, particularly in applications where the input signal has a low signal-to-noise ratio (SNR). The Phase Locked Loop (PLL) is a widely used method for extracting the frequency and phase of received signals in both stationary and high dynamic scenarios. However, the PLL's performance is limited by two factors: the trade-off between fast acquisition time and accurate phase extraction, and its poor performance for low SNR signals. To improve the understanding of this problem, this study conducts a review of the mathematical model of the PLL and explains the associated design challenges. After conducting a comprehensive literature review, the proposed solutions are introduced and evaluated. The solutions aimed at resolving the trade-off are classified into two categories: adaptive loop filter and frequency estimation algorithms assisted PLL. Their respective advantages and disadvantages are analysed, and based on this analysis, the frequency estimation algorithms assisted PLL category is selected for further improvement in PLL performance. Coherent integration is identified as the primary solution for low SNR inputs in both categories since the expected received frequency is already known.

This study introduces an innovative algorithm for real-time carrier tracking application, which combines a PLL with an accurate and fast frequency estimation algorithm (FFEA) based on the discrete Fourier transform (DFT). The proposed approach addresses the challenge of detecting low SNR signals by incorporating an adaptive DFT-length architecture within the FFEA. By leveraging the carrier frequency information provided by the FFEA, two significant contributions are achieved. Firstly, the signal passing through the PLL is effectively filtered, thereby improving SNR. Secondly, by assuming negligible frequency error for FFEA, the carrier frequency error between the input signal frequency and the VCO output frequency is effectively removed. Therefore, the function of the PLL, which encompasses both phase and frequency acquisition, is simplified to phase acquisition. As a result, the trade-off is greatly mitigated.

The proposed design has been implemented in MATLAB, and the results indicate a significant improvement in the performance of the traditional PLL under stationary conditions. Moreover, in high dynamic conditions, the proposed approach achieves a 66 percent reduction in acquisition time compared to the traditional frequency locked loop (FLL)-assisted PLL, with an RMSE of 2.15 Hz at -30dB SNR, while the traditional FLL-assisted PLL had an RMSE of 10.2 Hz at similar conditions. Additionally, the proposed design has been compared with three previously published designs that aim to enhance PLL performance under high dynamic conditions, and the results demonstrate that the proposed approach outperforms all three designs.