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Unified design flow for SiGe and group III-V broadband microwave integrated circuits utilising custom pcells

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posted on 2023-09-26, 06:38 authored by Leigh Eric Milner
The design and layout process for silicon-based (analogue) and group III-V based (microwave) integrated circuits have traditionally required very different approaches, for many decades. There remains a motivation to develop a `unified' method to construct these circuits so that designers with some experience in one technology can easily transcend to the other. A robust method is proposed that provides a fast design approach towards an estimated `best' solution, requiring shorter electromagnetic (EM) setup and solve times, producing fewer layout design rule errors, and faster circuit completion to final tapeout. Two significant areas are explored: 1) Layout abstraction is raised by the development of custom parametrised cells (pcells) which allow the circuit to be automatically drawn with much greater time efficiency and error free layout. Complete layout libraries (e.g. 20 to 30 pcells each) are developed in each process technology - silicon germanium (SiGe), gallium arsenide (GaAs) and gallium nitirde (GaN). The layout libraries provide what designers really need, rather than the very basic offerings from the foundry vendor design kits. 2) A methodical step model framework is developed that has unique steps 1 to 4 - behavioural model, schematic elements, electromagnetic parts, and electromagnetic block for separate objects in the design, rather than being applied for the whole design at once. The potential for inaccuracies by removing coupling boundaries is studied as a topic of interest and found to have minimal impact when objects are carefully partitioned. The `quality' of a design's implementation can then be estimated for the first time by a separate reviewer without prior discussion with the designer. The circuit design examples include a 30 to 40 GHz GaAs pre-amplifier, a 5 to 18 GHz GaN non-uniform distributed power amplifier, a 25 to 42 GHz SiGe upconverter, and a dc to 110 GHz hot-via interconnect.

History

Table of Contents

1 Introduction -- 2 Background -- 3 Estimation of the peak performance of a semiconductor process -- 4 Step model for parameter selection and assessment -- 5 Design technique for simultaneous broadband gain and linearity -- 6 Optimisation with large parameter sets for peak performance -- Precision layout of SiGe circuits by utilising custom pcells -- 8 Chip interconnect design with e-field annotation -- 9 Conclusions and recommendations -- A Object oriented design principles -- References

Notes

Additional Supervisor 4: Leonard Hall

Awarding Institution

Macquarie University

Degree Type

Thesis PhD

Degree

Doctor of Philosophy

Department, Centre or School

School of Engineering

Year of Award

2023

Principal Supervisor

Sudipta Chakraborty

Additional Supervisor 1

Simon Mahon

Additional Supervisor 2

Anthony Parker

Rights

Copyright: The Author Copyright disclaimer: https://www.mq.edu.au/copyright-disclaimer

Language

English

Extent

272 pages

Former Identifiers

AMIS ID: 257656

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