DCT architecture design for HEVC / H.265 video coding

H.265 / High Efficiency Video Codec (HEVC) is a relatively new codec that is poised to replace N.264 / AVC as the high definition coding standard. The Discrete Cosine Transform (DCT) is widely used for the compression of video frames and images, including use in HEVC. The document proposes an architecture that completes a two dimensional DCT (2D-DCT) that uses a smaller area or a smaller gate count than existing architectures, while maintaining a similar throughput. The architecture is based on the algorithm proposed by Meber et al for a reusable architecture. The architecture is written using VHDL hardware description language to construct One Dimensional DCT (1D-DCT) modules of 4, 8, 16 and 32 point lengths that are used twice in combination with a transpose unit to compute the 2D-DCT. The 1D-DCT modules that have a length greater than 4, use use a reusable architecture that incorporates the N/2 DCT module and shift-adders to compute the DCT more area efficient than the common matrix multiplication method. The architecture was synthesised with Synopsis Design Tools to produce an Application Specific Integrated Circuit (ASIC) that is able to encode HK UHD video files at 60 FPS in a real time frame while saving more than 66% in hardware area or number of logic gates.