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Digital image processing based on the residue number system

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posted on 28.03.2022, 23:43 by Azadeh Safari
This thesis presents the design, optimisation and physical implementation of a two-dimensional (2D) discrete wavelet transform (DWT) image processor using the residue number system (RNS), and examines it against an initial processor designed based on existing binary models. The original contributions of the proposed design include a low-complexity hardware architecture of the RNS-based filter banks, optimised transposition units, and exploitation of the multi-voltage scheme to reduce the power consumption. Modular adders and multipliers of the RNS-based filter banks are simplified to save on hardware complexity, while modular arithmetic and 6-bit dyadic-fraction filter coefficients are applied to improve the system performance. The proposed design is synthesised with the Synopsys 90 nm Generic Library (SAED90nmEDK) using the Synopsys synthesis and implementation tools. The synthesis results show that the proposed RNS-based processor is 23% faster than the initial processor. Another noteworthy result is that the total area of the RNS-based processor is less than the total area in the initial binary processor. It confirms that using the proposed architecture for RNS-based filter banks has saved on the hardware complexity and the system area requirement. The proposed RNS-based processor is implemented using the multi-voltage (MV) low power design (LPD) scheme to improve the power performance of the proposed processor. The power synthesis results show that using the multi-voltage scheme reduces the total power of the proposed RNS-based design by up to 50%. The proposed residue arithmetic units are explained in details to illustrate the novelty of the proposed design.


Table of Contents

1. Introduction -- 2. Review of image-compression algorithms and schemes -- 3. Discrete wavelet transform for image-processing applications -- 4. The residue number system -- 5. Scaling in the residue number system -- 6. Logic design and FPGA implementation of RNS-based DWT digital image processor -- 7. RTL-to-gate synthesis -- 8. Physical implementation using design compiler topographical technology in ASIC methodology -- 9. Thesis conclusion and recommendations for future work.


Bibliography: pages 239-255 Theoretical thesis.

Awarding Institution

Macquarie University

Degree Type

Thesis PhD


PhD, Macquarie University, Faculty of Science, Department of Engineering

Department, Centre or School

Department of Engineering

Year of Award


Principal Supervisor

Yinan Kong

Additional Supervisor 1

Sam Reisenfeld


Copyright Azadeh Safari 2014. Copyright disclaimer: http://www.copyright.mq.edu.au




1 online resource (xxviii, 255 pages) illustrqations (some colour)

Former Identifiers

mq:42640 http://hdl.handle.net/1959.14/1054806