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Ultra-low power FFT processor design for IoT devices

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posted on 2022-03-28, 16:48 authored by Reza Homainejad
In a world where sensor data can be collected through smart grid and sensor backup applications, reducing power consumption has become one of the most important factors for data transmission. FFT processing is capable of low power, high throughput sensor data collecting. The IEEE 802.11ah standard is designed with the physical layer (PHY) and the medium access control (MAC). This paper discusses developing an FFT processor for this new standard. A simulation of the FFT processor is created in MATLAB, along with a VHDL component that handles the FFT architecture. These two are then tested for competency and validity, before then testing each other for evaluation and results.


Table of Contents

Chapter 1. Introduction -- Chapter 2. The characteristics of IEEE 802.11ah WiFi standard and its requirements for an FFT processor -- Chapter 3. Fast Fourier Transform : the algorithms and architecture that define it -- Chapter 4. MATLAB and VHDL implementation -- Chapter 5. Verification and evaluation -- Conclusions and future work -- Abbreviations -- Appendices -- Bibliography.


Empirical thesis. Bibliography: pages 44-45

Awarding Institution

Macquarie University

Degree Type

Thesis bachelor honours


BSc (Hons), Macquarie University, Faculty of Science and Engineering, School of Engineering

Department, Centre or School

School of Engineering

Year of Award


Principal Supervisor

Ediz Cetin


Copyright Reza Homainejad 2017. Copyright disclaimer: http://mq.edu.au/library/copyright




1 online resource (xv, 45 pages diagrams, graphs, tables)

Former Identifiers

mq:70443 http://hdl.handle.net/1959.14/1263991

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