Ultra-low power FFT processor design for IoT devices

In a world where sensor data can be collected through smart grid and sensor backup applications, reducing power consumption has become one of the most important factors for data transmission. FFT processing is capable of low power, high throughput sensor data collecting. The IEEE 802.11ah standard is designed with the physical layer (PHY) and the medium access control (MAC). This paper discusses developing an FFT processor for this new standard. A simulation of the FFT processor is created in MATLAB, along with a VHDL component that handles the FFT architecture. These two are then tested for competency and validity, before then testing each other for evaluation and results.